1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming an erasable programmable read only memory (EEPROM).
2. Description of the Related Art
EPROM, an acronym for Erasable Programmable Read Only Memory, is the memory circuit that is most often used in computer and electronic products. One of its advantages is that neither the program, nor the data stored in the EPROM, are not lost under normal conditions. If there is a need to erase the stored program and data, it is simply exposed to an ultraviolet light source for a specified period of time. In this way, the EPROM can be reprogrammed again. However, the EPROM erase operation wipes out all the stored data residing within. Therefore, whenever a data update is required, every bit of data must be rewritten back to the EPROM, which is rather time-consuming. Technology for a flash EPROM was developed by Intel Corporation. The data does not need to be erased completely. Instead, the characteristic of the flash EPROM is to erase data block by block. Hence, the time for reprogramming a flash EPROM is reduced.
FIG. 1 is a top-view layout showing a conventional flash EPROM. In FIG. 1, the conventional flash EPROM includes an isolation structure 101, a floating gate layer 103, a control gate 105, a common source region 106, and a drain region 107.
FIGS. 2A through 2C are schematic, cross-sectional views of a portion of a semiconductor device showing the conventional steps of fabricating a flash EPROM. The (I) of each figure is a cross-sectional view of FIG. 1 taken along line I--I. The (II) of each figure is a cross-sectional view of FIG. 1 taken along line II--II. The (III) of each figure is a cross-sectional view of FIG. 1 taken along line III--III.
In FIG. 2A, a P-type substrate 100 having a shallow trench (STI) 101 therein is provided. A tunnel oxide layer 102 and a floating gate layer 103 are formed in sequence over the substrate 100, after which the tunnel oxide layer 102 and the floating gate layer 103 are patterned.
In FIG. 2B, a first isolation layer 104 and a control gate layer 105 are formed in sequence over the substrate 100. The control gate layer 105, the isolation layer 104, the floating gate layer 103, and the tunnel oxide layer 102 are patterned.
In FIG. 2C, an ion implantation step is performed to form a common source region 106 and drain regions 107 in the substrate 100. Spacers 108 are formed over the sidewalls of the control gate layer 105, the isolation layer 104, the floating gate layer 103, and the tunnel oxide layer 102. Then, a self-aligned silicide step is performed to form silicide layers 109 on the control gate layer 105, the common source region 106, and the drain region 107.
However, it is difficult to form the silicide layer 109 on an abrupt-step structure (show in FIG. 2B (II)) in the conventional process, in which the resistance of common source region 106 is increased. In FIG. 2A (II), the surface of the tunnel oxide layer 102 and the floating gate layer 103 is higher than the surface of substrate 100. Therefore the surface over the substrate 100 is not flat. In FIG. 2B (II), an abrupt-step surface 113 is formed after patterning the control gate layer 105, the isolation layer 104, the floating gate layer 103, and the tunnel oxide layer 102. In FIG. 2C (II), it is difficult to perform a self-aligned silicide step on the surface of an abrupt-step structure 114 to form the silicide layer 109 thereon. Therefore, the resistance of the common source region 106 is increased.